Vesdiam Technologies

AI-Powered Specification-to-RTL Generation. 

Transform hardware specifications into verified, reviewable Verilog
 

Vesdiam is developing an AI-assisted RTL engineering platform that converts natural-language specifications, architecture descriptions and interface requirements into Verilog.

The system generates RTL, compiles and simulates the design, analyses verification failures and iteratively improves the implementation—while keeping engineers in control.

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Benchmarks

• VerilogEval v2: 153/156, 98.1% Strict Pass@1
  Matches the best published result.

• RTLLM v2.1: 48/50, 96.0% Strict Pass@1
  First reported result on RTLLM v2.1.

• RealBench: 36/60, 60.0% Strict Pass@1

• 48.9% (22/45) on ChipBench
  Exceeds the previous best published model result of 45% (LocalLLV).